1. Field of the Invention
The present invention relates to a semiconductor memory array structure, and more particularly to a memory array having independent depth-controlled shallow trench isolation, and methods of manufacturing the same.
2. Description of the Prior Art
As well known in the art, a shallow trench isolation structure comprises a dielectric material that laterally surrounds active areas (AA) of a semiconductor substrate comprising a semiconductor material, which is typically silicon. Typically, the shallow trench isolation structure is formed by first patterning a shallow trench that laterally surrounds the active area, followed by deposition of a dielectric material into the shallow trench and a subsequent planarization of the deposited dielectric material. The dielectric material is typically removed from above the active areas during the planarization step, and the remaining portions of the dielectric material within the shallow trench constitute the shallow trench isolation structure.
Conventionally, the aforesaid shallow trench that laterally surrounds the active area is formed by using a single lithographic process and a single dry etching process. That is, only one photomask (i.e., AA photomask) that defines the AA pattern thereon is used during the lithographic process, and the shallow trench has substantially the same depth. However, due to the line shortening effect and/or other optical interference effects, the AA pattern transferred to the photoresist or the underlying substrate has an oval-like shape that has a smaller surface area than the original pattern that defined on the AA photomask. This adversely affects the process window and the electric performance of the semiconductor device fabricated in the AA regions.